The present invention relates to semiconductor device fabrication and, more specifically, to passive devices for fin-type field-effect transistor (FinFET) integrated circuit technologies, design structures for passive devices for use in FinFET integrated circuit technologies, and methods of fabricating passive devices for use in FinFET integrated circuit technologies.
A chip may be exposed to random electrostatic discharge (ESD) events that can direct potentially large and damaging ESD currents to the integrated circuits of the chip. Manufacturers, assemblers, and users of chips often take precautions to avoid causing ESD events or to militate against the effect of an ESD event. One such precaution is to incorporate an ESD prevention circuit into the chip. The ESD protection circuit prevents damage to the sensitive devices of the integrated circuits during post-manufacture handling. The ESD protection circuit may also function to protect the integrated circuits while the chip is installed on a circuit board or other carrier.
In the absence of an ESD event, the ESD protection circuit maintains an ESD protection device in a high-impedance, non-conductive state in which the ESD protection device is electrically isolated from the protected internal circuits. If an ESD event occurs, the ESD protection device is triggered by the ESD protection circuit to change from its non-conductive state to a low-impedance, conductive state. In its conductive state, the ESD protection device directs the ESD current to ground and away from the sensitive devices in the integrated circuits on the chip. The ESD protection device clamps the ESD protection device in its conductive state until the ESD current is drained and the ESD voltage is discharged to an acceptable level.
FinFETs are non-planar devices for use in an integrated circuit of a chip that are capable of being more densely packed than traditional planar complementary metal-oxide-semiconductor (CMOS) transistors. In addition, a FinFET also offers superior short channel scalability, reduced threshold voltage swing, higher mobility, and the ability to operate at lower supply voltages than traditional planar CMOS transistors. Each FinFET features a narrow vertical fin of semiconductor material and a gate electrode that intersects a central channel of the fin. A thin gate dielectric layer separates the gate electrode from the fin. Heavily-doped source and drain regions are formed at opposite ends of the fin and border the central channel.
Improved device structures, fabrication methods, and design structures are needed for passive devices in FinFET integrated circuit technologies.